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ordering number : enn*7980 92504tn (ot) no. 7980-1/39 overview the lc75857e and lc75857w are 1/3 duty and 1/4 duty lcd display drivers that can directly drive up to 164 segments and can control up to four general-purpose output ports. these products also incorporate a key scan circuit that accepts input from up to 30 keys to reduce printed circuit board wiring. features ? key input function for up to 30 keys (a key scan is performed only when a key is pressed.) ? 1/3 duty and 1/4 duty drive schemes can be controlled from serial data. ? 1/2 bias and 1/3 bias drive schemes can be controlled from serial data. ? capable of driving up to 126 segments using 1/3 duty and up to 164 segments using 1/4 duty. ? sleep mode and all segments off functions that are controlled from serial data. ? switching between key scan output and segment output can be controlled from the serial data. ? the key scan operation enabled/disabled state can be controlled from the serial data. ? switching between segment output port and general-purpose output port can be controlled from serial data. ? the common and segment output waveform frame frequency can be controlled from the serial data. ? switching between rc oscillator mode and external clock mode can be controlled from the serial data. ? serial data i/o supports ccb format communication with the system controller. ? direct display of display data without the use of a decoder provides high generality. ? independent v lcd for the lcd driver block. (when the logic block supply voltage v dd is in the range 3.6 to 6.0 v, v lcd can be set to a voltage in the range 0.75 v dd to 6.0 v, and when v dd is in the range 2.7 to 3.6 v, v lcd can be set to a voltage in the range 2.7 to 6.0 v.) ? provision of an on-chip voltage-detection type reset circuit prevents incorrect displays. sanyo semiconductors data sheet lc75857e lc75857w cmos ic 1/3, 1/4 duty lcd display drivers with key input function any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein. preliminary
no. 7980- 2 /39 lc75857e, lc75857w parameter symbol conditions ratings unit maximum supply voltage v dd max v dd e0.3 to +7.0 v v lcd max v lcd e0.3 to +7.0 v in 1 ce, cl, di e0.3 to +7.0 input voltage v in 2 osc,test e0.3 to v dd +0.3 v v in 3 v lcd 1, v lcd 2, ki1 to ki5 e0.3 to v lcd +0.3 v out 1 do e0.3 to +7.0 output voltage v out 2 osc e0.3 to v dd +0.3 v v out 3 s1 to s42, com1 to com4, ks1 to ks6, p1 to p4 e0.3 to v lcd +0.3 i out 1 s1 to s42 300 a output current i out 2 com1 to com4 3 i out 3 ks1 to ks6 1 ma i out 4 p1 to p4 5 allowable power dissipation pd max ta = 85 ? c 200 mw operating temperature topr e40 to +85 ? c storage temperature tstg e55 to +125 ? c specifications absolute maximum ratings at ta=25 ? c, v ss =0v parameter symbol conditions ratings unit min typ max v dd v dd 2.7 6.0 supply voltage v lcd v lcd : v dd = 3.6 v to 6.0 v 0.75 v dd 6.0 v v lcd : v dd = 2.7 v to 3.6 v 2.7 6.0 input voltage v lcd 1 v lcd 1 2/3 v lcd v lcd v v lcd 2 v lcd 2 1/3 v lcd v lcd v ih 1 ce, cl, di 0.8 v dd 6.0 input high level voltage v ih 2 ki1 to ki5 0.6 v lcd v lcd v v ih 3 osc: external clock mode 0.7 v dd v dd v il 1 ce, cl, di 0 0.2 v dd input low level voltage v il 2 ki1 to ki5 0 0.2 v lcd v v il 3 osc: external clock mode 0 0.3 v dd recommended rc oscillator external resistor r osc osc: rc oscillator mode 39 k recommended rc oscillator external capacitor c osc osc: rc oscillator mode 1000 pf guaranteed rc oscillator operating range f osc osc: rc oscillator mode 19 38 76 khz external clock frequency f ck osc: external clock mode :figure 4 19 38 76 khz external clock duty d ck osc: external clock mode :figure 4 30 50 70 % data setup time t ds cl, di :figures 2,3 160 ns data hold time t dh cl, di :figures 2,3 160 ns ce wait time t cp ce, cl :figures 2,3 160 ns ce setup time t cs ce, cl :figures 2,3 160 ns ce hold time t ch ce, cl :figures 2,3 160 ns high level clock pulse width t? h cl :figures 2,3 160 ns low level clock pulse width t? l cl :figures 2,3 160 ns rise time t r ce, cl, di :figures 2,3 160 ns fall time t f ce, cl, di :figures 2,3 160 ns do output delay time t dc do r pu =4.7 k , c l =10pf * 1 :figures 2,3 1.5 s do rise time t dr do r pu =4.7 k , c l =10pf * 1 :figures 2,3 1.5 s allowable operating ranges at ta = C40 to +85 c, v ss =0v note: * 1. since do is an open-drain output, these values depend on the resistance of the pull-up resistor r pu and the load capacitance c l .
no. 7980- 3 /39 lc75857e, lc75857w parameter symbol conditions ratings unit min typ max hysteresis v h1 ce, cl, di 0.1 v dd v v h2 ki1 to ki5 0.1 v lcd power-down detection voltage v det 2.0 2.2 2.4 v input high level current i ih 1 ce, cl, di: v i = 6.0 v 5.0 a i ih 2 osc: v i = v dd external clock mode 5.0 input low level current i il 1 ce, cl, di: v i = 0 v e5.0 a i il 2 osc: v i = 0 v external clock mode e5.0 input floating voltage v if ki1 to ki5 0.05 v lcd v pull-down resistance r pd ki1 to ki5: v lcd = 5.0 v 50 100 250 k ki1 to ki5: v lcd = 3.0 v 100 200 500 output off leakage current i offh do: vo = 6.0 v 6.0 a v oh 1 ks1 to ks6: i o = C500 a v lcd = 3.6 to 6.0 v v lcd C 1.0 v lcd C 0.5 v lcd C 0.2 ks1 to ks6: i o = C250 a v lcd = 2.7 to 3.6 v v lcd C 0.8 v lcd C 0.4 v lcd C 0.1 output high level voltage v oh 2 p1 to p4: i o = C1 ma v lcd C 0.9 v v oh 3 s1 to s42: i o = C20 a v lcd C 0.9 v oh 4 com1 to com4: i o = C100 a v lcd C 0.9 v ol 1 ks1 to ks6: i o = 25 a v lcd = 3.6 to 6.0 v 0.2 0.5 1.5 ks1 to ks6: i o = 12.5 a v lcd = 2.7 to 3.6 v 0.1 0.4 1.2 output low level voltage v ol 2 p1 to p4: i o = 1 ma 0.9 v v ol 3 s1 to s42: i o = 20 a 0.9 v ol 4 com1 to com4: i o = 100 a 0.9 v ol 5 do: i o = 1 ma 0.1 0.5 v mid 1 com1 to com4: 1/2 bias, i o = 100 a 1/2 v lcd C 0.9 1/2 v lcd + 0.9 v mid 2 s1 to s42: 1/3 bias,i o = 20 a 2/3 v lcd C 0.9 2/3 v lcd + 0.9 output middle level voltage * 2 v mid 3 s1 to s42: 1/3 bias, i o = 20 a 1/3 v lcd C 0.9 1/3 v lcd + 0.9 v v mid 4 com1 to com4: 1/3 bias,i o = 100 a 2/3 v lcd C 0.9 2/3 v lcd + 0.9 v mid 5 com1 to com4: 1/3 bias,i o = 100 a 1/3 v lcd C 0.9 1/3 v lcd + 0.9 oscillator frequency fosc osc: r osc = 39 k , c osc = 1000 pf 30.4 38 45.6 khz i dd 1 v dd :sleep mode 100 i dd 2 v dd : v dd = 6.0 v, output open,fosc = 38 khz 300 600 current drain i lcd 1 v lcd : sleep mode 5 a i lcd 2 v lcd : v lcd = 6.0 v, output open, 1/2 bias, 100 200 fosc = 38 khz i lcd 3 v lcd : v lcd = 6.0 v, output open, 1/3 bias, 60 120 fosc = 38 khz electrical characteristics for the allowable operating ranges nete: * 2. excluding the bias voltage generation divider resistor built into v lcd 1 and v lcd 2. (see figure 1.) 14.0 17.2 14.0 17.2 0.15 0.35 0.8 (2.7) 3.0max 0.1 0.8 (1.0) 1 16 17 32 33 48 49 64 sanyo: qip64e [lc75857e] 10.0 10.0 12.0 12.0 0.15 0.5 (1.5) .1 1.7max 0.18 ( 0.5) ( 1.25) 1 16 17 32 33 48 49 64 sanyo: sqfp64 [lc75857w] p ac ka g e dimensions unit: mm 3159a-qip64e unit: mm 3190a-sqfp64
figure 1 1. serial data i/o timing when cl is stopped at the low level figure 3 no. 7980- 4 /39 lc75857e, lc75857w v lcd v lcd 2 v lcd 1 tdh 50% vih1 vih1 vil 1 vil 1 vih1 vil 1 tdr tdc tch tcs tcp tds tr cl t l t h tf do di d1 d0 ce 2. serial data i/o timing when cl is stopped at the high level 50% vih1 vil 1 tdh vih1 vil 1 vih1 vil 1 tdr tdc tch tcs tcp tds tf cl t h t l tr do di d1 d0 ce to the common segment driver excluding these registors. figure 2 figure 4 3. osc pin clock timing in external clock mode vih3 vil3 osc t ck l t ck h f ck = 1 t ck h + t ck l [khz] d ck = t ck h t ck h + t ck l 100[%] 50%
pin assignments no. 7980- 5 /39 lc75857e, lc75857w vdd vlcd2 p4/s4 ks2/s41 p3/s3 s5 p2/s2 p1/s1 ki1 lc75857e/w ki2 vlcd vlcd1 vss osc s17 33 48 32 49 17 64 16 1 ki3 ki4 ki5 do ce cl di s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s31 s32 ks6 ks5 ks4 ks3/s42 ks1/s40 com1 com2 com3 com4/s39 s38 s37 s36 s35 s34 s33 test top view
block diagram no. 7980- 6 /39 lc75857e, lc75857w vdet ccb interface com4/s39 com3 com2 com 1 common driver clock generator vss vlcd2 vlcd 1 vlcd ce vdd di test cl do osc ki5 ki4 ki3 ki2 ki1 ks6 ks5 ks4 s42/ks3 s41/ks2 s40/ks 1 key scan key buffer control register segment driver & latch s 1 /p 1 s2/p2 s4/p4 s5 s38 s3/p3 shift register
no. 7980- 7 /39 lc75857e, lc75857w pin pin no. function active i/o handling when unused ? o open com1 to ? o open com3 com4/s39 ks1/s40 43 ks2/s41 44 ? o open ks3/s42 45 ks4 to ks6 46 to 48 ki1 to ki5 49 to 53 h i gnd osc 60 ? i/o v dd ce 62 h i cl 63 i gnd di 64 ? i do 61 ? o open test 59 this pin must be connected to ground. ? i ? v lcd 1 56 ? i open v lcd 2 57 ? i open v dd 54 ? ? ? v lcd 55 ? ? ? v ss 58 power supply connection. connect to ground. ? ? ? pin functions segment outputs for displaying the display data transferred by serial data input. the s1/p1 to s4/p4 pins can be used as general-purpose output ports under serial data control. common driver outputs the frame frequency is fo [hz] the com4/s39 pin can be used as a segment output in 1/3 duty. key scan outputs although normal key scan timing lines require diodes to be inserted in the timing lines to prevent shorts, since these outputs are unbalanced cmos transistor outputs, these outputs will not be damaged by shorting when these outputs are used to form a key matrix. the ks1/s40 to ks3/s42 pins can be used as segment outputs when so specified by the control data. key scan inputs these pins have built-in pull-down resistors. the osc pin can be used to form an oscillator circuit with an external resistor and an external capacitor. if external clock mode is selected with the control data, this pin is used to input an external clock signal. serial data interface connections to the controller. note that do, being an open-drain output, requires a pull-up resistor. ce :chip enable cl :synchronization clock di :transfer data do :output data used for applying the lcd drive 2/3 bias voltage externally. must be connected to v lcd 2 when a 1/2 bias drive scheme is used. used for applying the lcd drive 1/3 bias voltage externally. must be connected to v lcd 1 when a 1/2 bias drive scheme is used. logic block power supply connection. provide a voltage of between 2.7 and 6.0v. lcd driver block power supply connection. a voltage in the range 0.75 vdd to 6.0 v must be provided when vdd is in the range 3.6 to 6.0 v, and a voltage in the range 2.7 v to 6.0 v must be provided when vdd is in the range 2.7 to 3.6 v. s1/p1 to s4/p4 s5 to s38 1 to 4 5 to 38 42 to 40 39
serial data input 1. 1/3 duty (1) when cl is stopped at the low level note: b0 to b3, a0 to a3 ...... ccb address dd ................................ direction data no. 7980- 8 /39 lc75857e, lc75857w a3 b0 0 0 dr sc p2 p 1 p0 k 1 k0 kc 1 kc 0 dt d42 d41 d2 d1 1 1 0 dd do di cl ce 0 kc2 ksc 0c 0 0 0 0 0 b1 b2 b3 a2 a 1 a0 0 0 s p fc0 fc 1 fc2 a0 b0 1 d44 d43 1 1 0 dd d83 d84 0 b 1 b2 a 1 a2 a3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 a0 b0 1 d126 d125 d86 d85 1 1 0 dd 0 0 0 0 0 0 b 1 b2 a 1 a2 a3 0 b3 b3 display data control data fixed data display data fixed data display data
no. 7980- 9 /39 lc75857e, lc75857w (2) when cl is stopped at the high level note: b0 to b3, a0 to a3 ...... ccb address dd ................................ direction data ccb address ............ 42h d1 to d126 .............. display data sp ............................ normal mode/sleep mode control data kc0 to kc2 .............. key scan output state setting data ksc .......................... key scan operation enabled/disabled state setting data k0, k1 ...................... key scan output/segment output selection data p0 to p2 .................. segment output port/general-purpose output port selection data sc ............................ segment on/off control data dr ............................ 1/2 bias or 1/3 bias drive selection data dt ............................ 1/3 duty or 1/4 duty drive selection data fc0 to fc2 .............. common and segment output waveform frame frequency setting data oc ............................ rc oscillator mode/external clock mode switching selection data d2 d1 1 1 0 0 0 0 0 dd do di cl ce 0 d43 d44 1 1 0 dd 0 0 0 0 0 b0 dd b1 b2 b3 a0 a1 a2 a3 b0 b1 b2 b3 a0 a1 a2 a3 b0 b1 b2 b3 a0 a1 a2 a3 0 0 dr sc p2 p 1 p0 k 1 k0 kc 1 kc0 dt d42 d41 0 kc2 ksc 0c 0 0 s p fc0 fc 1 fc2 1 d83 d84 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 d126 d125 d86 d85 1 1 0 0 0 0 0 0 0 0 display data control data fixed data display data display data fixed data
no. 7980- 10 /39 lc75857e, lc75857w 2. 1/4duty (1) when cl is stopped at the low level note: b0 to b3, a0 to a3 ...... ccb address dd ................................ direction data dd do di cl ce dd dd dd d1 1 1 0 0 0 0 0 0 b0 b1 b2 b3 a0 a1 a2 a3 b0 b1 b2 b3 a0 a1 a2 a3 b0 b1 b2 b3 a0 a1 a2 a3 b0 b1 b2 b3 a0 a1 a2 a3 0 0 dr sc p2 p 1 p0 k 1 k0 kc 1 kc0 dt d42 d41 d40 d43 kc2 ksc 0c d44 0 s p fc0 fc 1 fc2 d45 1 1 0 0 0 0 0 0 d85 1 1 0 0 0 0 0 0 d125 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d84 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 d124 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 d164 1 display data control data fixed data display data display data display data fixed data fixed data
no. 7980- 11 /39 lc75857e, lc75857w (2) when cl is stopped at the high level note: b0 to b3, a0 to a3 ...... ccb address dd ................................ direction data ccb address ............ 42h d1 to d164 .............. display data sp ............................ normal mode/sleep mode control data kc0 to kc2 .............. key scan output state setting data ksc .......................... key scan operation enabled/disabled state setting data k0, k1 ...................... key scan output/segment output selection data p0 to p2 .................. segment output port/general-purpose output port selection data sc ............................ segment on/off control data dr ............................ 1/2 bias or 1/3 bias drive selection data dt ............................ 1/3 duty or 1/4 duty drive selection data fc0 to fc2 .............. common and segment output waveform frame frequency setting data oc ............................ rc oscillator mode/external clock mode switching selection data dd do di cl ce dd dd dd d1 1 1 0 0 0 0 0 0 b0 b1 b2 b3 a0 a1 a2 a3 0 0 dr sc p2 p 1 p0 k 1 k0 kc 1 kc0 dt d42 d41 d40 d43 kc2 ksc 0c d44 0 sp fc0 fc 1 fc2 b0 b1 b2 b3 a0 a1 a2 a3 d45 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d84 1 b0 b1 b2 b3 a0 a1 a2 a3 d85 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 d124 0 b0 b1 b2 b3 a0 a1 a2 a3 d125 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 d164 1 display data control data fixed data display data display data display data fixed data fixed data
control data functions 1. sp : normal mode/sleep mode control data this control data bit switches the ic between normal mode and sleep mode. note: see the descriptions of the kc- to kc2, ksc, k0, k1, and p0 to p2 bits in the control data for details on setting the key scan operating state and setting the general-purpose output port state. no. 7980- 12 /39 lc75857e, lc75857w sp mode osc pin state common and segment key scan general-purpose rc oscillator mode external clock mode pin output states operating state output port states 0 normal oscillator operating external clock signal accepted lcd drive waveforms are output 1 sleep oscillator stopped acceptance of the external the state can be set the state can be set (the oscillator operates clock signal is disabled. l (vss) during key scan operations.) (the external clock signal is accepted during key scan operations) 2. kc0 to kc2 : key scan output state setting data these control data bits set the states of the key scan output pins ks1 to ks6. note: this assumes that the ks1/s40 to ks3/s42 output pins are selected for key scan output. also note that key scan output signals are not output from output pins that are set to the low level. control data output pin states during key scan standby kc0 kc1 kc2 ks1 ks2 ks3 ks4 ks5 ks6 0 0 0 h h h h h h 0 0 1 l h h h h h 0 1 0 l l h h h h 0 1 1 l l l h h h 1 0 0 l l l l h h 1 0 1 l l l l l h 1 1 0 l l l l l l 3. ksc : key scan operation enabled/disabled state setting data this control data bit enables or disables key scan operation. ksc key scan operating state 0 key scan operation enabled (a key scan operation is performed if any key on the lines corresponding to ks1 to ks6 pin which is set high is pressed .) 1 key scan operation disabled (no key scan operation is performed, even if any of the keys in the key matrix are pressed. if this state is set up, the key da ta is forcibly reset to 0 and the key data read request is also cleared. (do is set high.)) 4. k0, k1 : key scan output /segment output selection data these control data bits switch the functions of the ks1/s40 to ks3/s42 output pins between key scan output and segment output. note: ksn(n = 1 to 3) : key scan output sn (n = 40 to 42): segment output control data output pin state maximum number of k0 k1 ks1/s40 ks2/s41 ks3/s42 input keys 0 0 ks1 ks2 ks3 30 0 1 s40 ks2 ks3 25 1 0 s40 s41 ks3 20 1 1 s40 s41 s42 15
no. 7980- 13 /39 lc75857e, lc75857w 5. p0 to p2 : segment output port/general-purpose output port selection data these control data bits switch the functions of the s1/p1 to s4/p4 output pins between the segment output port and the general-purpose output port. control data output pin state p0 p1 p2 s1/p1 s2/p2 s3/p3 s4/p4 0 0 0 s1 s2 s3 s4 0 0 1 p1 s2 s3 s4 0 1 0 p1 p2 s3 s4 0 1 1 p1 p2 p3 s4 1 0 0 p1 p2 p3 p4 note: sn(n=1 to 4): segment output port pn(n=1 to 4): general-purpose output port the table below lists the correspondence between the display data and the output pins when these pins are selected to be general-purpose output ports. for example, if the circuit is operated in 1/4 duty and the s4/p4 output pin is selected to be a general-purpose output port, the s4/p4 output pin will output a high level (v lcd ) when the display data d13 is 1, and will output a low level (vss) when d13 is 0. output pin corresponding display data 1/3 duty 1/4 duty s1/p1 d1 d1 s2/p2 d4 d5 s3/p3 d7 d9 s4/p4 d10 d13 however, note that when the segments are turned off by setting sc to 1, the segments are turned off by outputting segment off waveforms from the segment output pins. sc display state 0 on 1 off 6. sc : segment on/off control data this control data bit controls the on/off state of the segments. dr bias drive scheme 0 1/3 bias drive 1 1/2 bias drive 7. dr : 1/2 bias or 1/3 bias drive selection data this control data bit switches between lcd 1/2 bias or 1/3 bias drive. dt duty drive scheme output pin state (com4/s39) 0 1/4 duty drive com4 1 1/3 duty drive s39 8. dt : 1/3 duty or 1/4 duty drive selection data this control data bit switches between lcd 1/3 duty or 1/4 duty drive. note: com4: common output s39 : segment output
no. 7980- 14 /39 lc75857e, lc75857w 9. fc0 to fc2 : common and segment output waveform frame frequency setting data these control data bits set the common and segment output waveform frequency. control data frame frequency, fo (hz) fc0 fc1 fc2 0 0 0 f osc /768, f ck /768 0 0 1 f osc /576, f ck /576 0 1 0 f osc /384, f ck /384 0 1 1 f osc /288, f ck /288 1 0 0 f osc /192, f ck /192 10. oc : rc oscillator mode/external clock mode switching selection data this control data bit selects the osc pin function (rc oscillator mode or external clock mode). oc osc pin function 0 rc oscillator mode 1 external clock mode note: if rc oscillator mode is selected, connect an external resistor rosc and an external capacitor cosc to the osc pin. display data and output pin correspondence 1. 1/3 duty note: this is for the case where the output pins s1/p1 to s4/p4, com4/s74, ks1/s40 to ks3/s42 are selected for use as segment o utputs. output pin com1 com2 com3 s1/p1 d1 d2 d3 s2/p2 d4 d5 d6 s3/p3 d7 d8 d9 s4/p4 d10 d11 d12 s5 d13 d14 d15 s6 d16 d17 d18 s7 d19 d20 d21 s8 d22 d23 d24 s9 d25 d26 d27 s10 d28 d29 d30 s11 d31 d32 d33 s12 d34 d35 d36 s13 d37 d38 d39 s14 d40 d41 d42 s15 d43 d44 d45 s16 d46 d47 d48 s17 d49 d50 d51 s18 d52 d53 d54 s19 d55 d56 d57 s20 d58 d59 d60 s21 d61 d62 d63 output pin com1 com2 com3 s22 d64 d65 d66 s23 d67 d68 d69 s24 d70 d71 d72 s25 d73 d74 d75 s26 d76 d77 d78 s27 d79 d80 d81 s28 d82 d83 d84 s29 d85 d86 d87 s30 d88 d89 d90 s31 d91 d92 d93 s32 d94 d95 d96 s33 d97 d98 d99 s34 d100 d101 d102 s35 d103 d104 d105 s36 d106 d107 d108 s37 d109 d110 d111 s38 d112 d113 d114 com4/s39 d115 d116 d117 ks1/s40 d118 d119 d120 ks2/s41 d121 d122 d123 ks3/s42 d124 d125 d126 for example, the table below lists the segment output states for the s11 output pin. display data output pin state (s11) d31 d32 d33 0 0 0 the lcd segments for com1, com2 and com3 are off. 0 0 1 the lcd segment for com3 is on. 0 1 0 the lcd segment for com2 is on. 0 1 1 the lcd segments for com2 and com3 are on. 1 0 0 the lcd segment for com1 is on. 1 0 1 the lcd segments for com1 and com3 are on. 1 1 0 the lcd segments for com1 and com2 are on. 1 1 1 the lcd segments for com1, com2 and com3 are on.
no. 7980- 15 /39 lc75857e, lc75857w 2. 1/4 duty output pin com1 com2 com3 com4 s1/p1 d1 d2 d3 d4 s2/p2 d5 d6 d7 d8 s3/p3 d9 d10 d11 d12 s4/p4 d13 d14 d15 d16 s5 d17 d18 d19 d20 s6 d21 d22 d23 d24 s7 d25 d26 d27 d28 s8 d29 d30 d31 d32 s9 d33 d34 d35 d36 s10 d37 d38 d39 d40 s11 d41 d42 d43 d44 s12 d45 d46 d47 d48 s13 d49 d50 d51 d52 s14 d53 d54 d55 d56 s15 d57 d58 d59 d60 s16 d61 d62 d63 d64 s17 d65 d66 d67 d68 s18 d69 d70 d71 d72 s19 d73 d74 d75 d76 s20 d77 d78 d79 d80 s21 d81 d82 d83 d84 output pin com1 com2 com3 com4 s22 d85 d86 d87 d88 s23 d89 d90 d91 d92 s24 d93 d94 d95 d96 s25 d97 d98 d99 d100 s26 d101 d102 d103 d104 s27 d105 d106 d107 d108 s28 d109 d110 d111 d112 s29 d113 d114 d115 d116 s30 d117 d118 d119 d120 s31 d121 d122 d123 d124 s32 d125 d126 d127 d128 s33 d129 d130 d131 d132 s34 d133 d134 d135 d136 s35 d137 d138 d139 d140 s36 d141 d142 d143 d144 s37 d145 d146 d147 d148 s38 d149 d150 d151 d152 ks1/s40 d153 d154 d155 d156 ks2/s41 d157 d158 d159 d160 ks3/s42 d161 d162 d163 d164 note: this is for the case where the output pins s1/p1 to s4/p4, ks1/s40 to ks3/s42 are selected for use as segment outputs. for example, the table below lists the segment output states for the s11 output pin. display data output pin state (s11) d41 d42 d43 d44 0 0 0 0 the lcd segments for com1,com2,com3 and com4 are off. 0 0 0 1 the lcd segment for com4 is on. 0 0 1 0 the lcd segment for com3 is on. 0 0 1 1 the lcd segments for com3 and com4 are on. 0 1 0 0 the lcd segment for com2 is on. 0 1 0 1 the lcd segments for com2 and com4 are on. 0 1 1 0 the lcd segments for com2 and com3 are on. 0 1 1 1 the lcd segments for com2,com3 and com4 are on. 1 0 0 0 the lcd segment for com1 is on. 1 0 0 1 the lcd segments for com1 and com4 are on. 1 0 1 0 the lcd segments for com1 and com3 are on. 1 0 1 1 the lcd segments for com1,com3 and com4 are on. 1 1 0 0 the lcd segments for com1 and com2 are on. 1 1 0 1 the lcd segments for com1,com2 and com4 are on. 1 1 1 0 the lcd segments for com1,com2 and com3 are on. 1 1 1 1 the lcd segments for com1,com2,com3 and com4 are on.
no. 7980- 16 /39 lc75857e, lc75857w serial data output 1. when cl is stopped at the low level note: b0 to b3, a0 to a3ccb address ce a3 a2 a1 a0 b3 b2 b1 b0 kd2 kd1 x sa kd30 kd29 kd28 kd27 0 1 0 0 0 0 1 1 do di cl x: don't care 2. when cl is stopped at the high level note: b0 to b3, a0 to a3ccb address ccb address ...... 43h kd1 to kd30 ........ key data sa ........................ sleep acknowledge data ce a3 a2 a1 a0 b3 b2 b1 b0 kd3 kd2 kd1 x x sa kd30 kd29 kd28 0 1 0 0 0 0 1 1 do di cl x: don't care note: if a key data read operation is executed when do is high, the read key data (kd1 to kd30) and sleep acknowledge data(sa) will b e invalid. output data output data
no. 7980- 17 /39 lc75857e, lc75857w sleep mode functions sleep mode is set up by setting sp in the control data to 1. when sleep mode is set up, both the segment and the common outputs will go to the low level. in rc oscillator mode (oc = 0), the oscillator on the osc pin will stop (although it will operate during key scan operations), and in external clock mode (oc = 1), the external clock signal reception on the osc pin will stop (although the clock signal will be received during key scan operations). thus this mode reduces power consumption. however, the s1/p1 to s4/p4 output pins can be used as general-purpose output ports under control of the p0 to p2 bits in the control data even in sleep mode. sleep mode is cancelled by setting sp in the control data to 0. output data 1. kd1 to kd30 : key data when a key matrix of up to 30 keys is formed from the ks1 to ks6 output pins and the ki1 to ki5 input pins and one of those keys is pressed, the key output data corresponding to that key will be set to 1. the table shows the relationship between those pins and the key data bits. when the ks1/s40 and ks2/s41 output pins are selected to be segment outputs by control data bits k0 and k1 and a key matrix of up to 20 keys is formed using the ks3/s42,ks4 to ks6 output pins and the ki1 to ki5 input pins, the kd1 to kd10 key data bits will be set to 0. 2. sa : sleep acknowledge data this output data bit is set to the state when the key was pressed. also, while do will be low in this case, if serial data is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. sa will be 1 in sleep mode and 0 in normal mode. ki1 ki2 ki3 ki4 ki5 ks1/s40 kd1 kd2 kd3 kd4 kd5 ks2/s41 kd6 kd7 kd8 kd9 kd10 ks3/s42 kd11 kd12 kd13 kd14 kd15 ks4 kd16 kd17 kd18 kd19 kd20 ks5 kd21 kd22 kd23 kd24 kd25 ks6 kd26 kd27 kd28 kd29 kd30
2. normal mode, when key scan operations are enabled the ks1 to ks6 pins are set to the high or low level by the kc0 to kc2 bits in the control data. (see the description of the control data.) when any key on the lines corresponding to ks1 to ks6 pin which is set high is pressed, a key scan is performed. keys are scanned until all keys are released. multiple key presses are recognized by determining whether multiple key data bits are set. if a key is pressed for longer than 615 t (s) (where t= = ) the lc75857e/w outputs a key data read request (a low level on do) to the controller. the controller acknowledges this request and reads the key data. however, if ce is high during a serial data transfer, do will be set high. after the controller reads the key data, the key data read request is cleared (do is set high) and the lc75857e/w performes another key scan. also note that do, being an open-drain output, requires a pull-up resistor (between 1 to 10 k ). no. 7980- 18 /39 lc75857e, lc75857w key on 576t[s] * 3 * 3 * 3 * 3 * 3 * 3 * 3 * 3 * 3 1 1 2 2 3 3 4 4 5 5 6 6 ks5 ks4 ks3 ks6 ks2 ks1 * 3 t= 1 fosc = 1 * 3 * 3 f ck key address di do ce 615t[s] 615t[s] 615t[s] t= 1 fosc = 1 f ck serial data transfer (ksc = 0) serial data transfer (ksc = 0) serial data transfer (ksc = 0) key input 1 key input 2 key scan key data read request key data read request key data read request key data read key data read key data read key address key address (43h) note: *3. these are set to the high or low level by the kc0 to kc2 bits in the control data. key scan output signals are not output f rom pins that are set to the low level. 1 f ck key scan operation functions 1. key scan timing the key scan period is 288t(s). to reliably determine the on/off state of the keys, the lc75857e/w scans the keys twice and determines that a key has been pressed when the key data agrees. it outputs a key data read request (a low level on do) 615t(s) after starting a key scan. if the key data dose not agree and a key was pressed at that point, it scans the keys again. thus the lc75857e/w cannot detect a key press shorter than 615t(s). 1 fosc
no. 7980- 19 /39 lc75857e, lc75857w 3. sleep mode, when key scan operations are enabled the ks1 to ks6 pins are set to the high or low level by the kc0 to kc2 bits in the control data. (see the description of the control data.) when any key on the lines corresponding to ks1 to ks6 pin which is set high is pressed, either the osc pin oscillator starts (if the ic is in rc oscillator mode) or the ic starts accepting the external clock signal (if the ic is in external clock mode), a key scan is performed. keys are scanned until all keys are released. multiple key presses are recoghized by determinig whether multiple key data bits are set. if a key is pressed for longer than 615t(s)(where t= = ) the lc75857e/w outputs a key data read request (a low level on do) to the controller. the controller acknowledges this request and reads the key data. however, if ce is high during a serial data transfer, do will be set high. after the controller reads the key data, the key data read request is cleared (do is set high) and the lc75857e/w performs another key scan. however, this dose not clear sleep mode. also note that do, being an open-drain output, requires a pull-up resistor (between 1 and 10 k ). ? sleep mode key scan example example: kc0 = 1, kc1 = 0, kc2 = 1, (sleep with only ks6 high) ki1 ki2 ki3 ki4 ki5 * 4 [l] ks1 [l] ks2 [l] ks3 [l] ks4 [l] ks5 [h] ks6 do di ce 615t[s] 615t[s] t= 1 fosc = 1 f ck key input (ks6 line) key scan serial data transfer (ksc = 0) serial data transfer (ksc = 0) serial data transfer (ksc = 0) key address (43h) key address key data read key data read key data read request key data read request 1 fosc note: * 4. these diodes are required to reliable recognize multiple key presses on the ks6 line when sleep mode state with only ks6 high, as in the above example. that is, these diodes prevent incorrect operations due to sneak currents in the ks6 key scan output signal when keys o n the ks1 to ks5 lines are pressed at the same time. when any one of these keys is pressed, either the osc pin oscillator starts (if the ic is in rc oscillator mode) or the ic starts accepting the external clock signal (if the ic is in external clock mode) and a key scan operation is performed. 1 f ck
multiple key presses although the lc75857e/w is capable of key scanning without inserting diodes for dual key presses, triple key presses on the ki1 to ki5 input pin lines, or multiple key presses on the ks1 to ks6 output pin lines, multiple presses other than these cases may result in keys that were not pressed recognized as having been pressed. therefore, a diode must be inserted in series with each key. applications that do not recognize multiple key presses of three or more keys should check the key data for three or more 1 bits and ignore such data. no. 7980- 20 /39 lc75857e, lc75857w 4. normal/sleep mode, when key scan operations are disabled the ks1 to ks6 pins are set to the high or low level by the kc0 to kc2 bits in the control data. no key scan operation is performed, whichever key is pressed. if the key scan disabled state (ksc = 1 in the control data) is set during a key scan, the key scan is stopped. if the key scan disabled state (ksc = 1 in the control data) is set when a key data read request (a low level on do) is output to the controller, all the key data is set to 0 and the key data read request is cleared (do is set high). note that do, being an open-drain output, requires a pull-up resister (between 1 to 10 k ). ? the key scan disabled state is cleared by setting ksc in the control data to 0. do di ce 6 15t[s] 6 15t[s] t = = 1 fosc 1 f ck key input 1 key input 2 key scan serial data transfer (ksc = 0) serial data transfer (ksc = 0) serial data transfer (ksc = 0) serial data transfer (ksc = 1) serial data transfer (ksc = 1) key address (43h) key data read request key data read request key data read
com1 1/3 duty, 1/2 bias drive technique com2 com3 lcd driver output when all lcd segments corresponding to com1, com2 and com3 are turned off. lcd driver output when only lcd segments corresponding to com1 are on lcd driver output when only lcd segments corresponding to com2 are on. lcd driver output when lcd segments corresponding to com1 and com2 are on. lcd driver output when only lcd segments corresponding to com3 are on. lcd driver output when lcd segments corresponding to com1 and com3 are on. lcd driver output when lcd segments corresponding to com2 and com3 are on. lcd driver output when all lcd segments corresponding to com1, com2 and com3 are on. 1/3 duty, 1/2 bias waveforms no. 7980- 21 /39 lc75857e, lc75857w vlcd vlcd1,vlcd2 0v fo[hz] vlcd vlcd1,vlcd2 0v vlcd vlcd1,vlcd2 0v vlcd vlcd1,vlcd2 0v vlcd vlcd1,vlcd2 0v vlcd vlcd1,vlcd2 0v vlcd vlcd1,vlcd2 0v vlcd vlcd1,vlcd2 0v vlcd vlcd1,vlcd2 0v vlcd vlcd1,vlcd2 0v vlcd vlcd1,vlcd2 0v note: when fc0 = 0, fc1 = 0, and fc2 = 0 in the control data f 0 = = f osc 768 f ck 768 when fc0 = 0, fc1 = 0, and fc2 = 1 in the control data f 0 = = f osc 576 f ck 576 when fc0 = 0, fc1 = 1, and fc2 = 0 in the control data f 0 = = f osc 384 f ck 384 when fc0 = 0, fc1 = 1, and fc2 = 1 in the control data f 0 = = f osc 288 f ck 288 when fc0 = 1, fc1 = 0, and fc2 = 0 in the control data f 0 = = f osc 192 f ck 192
no. 7980- 22 /39 lc75857e, lc75857w com1 1/3 duty, 1/3 bias drive technique com2 com3 lcd driver output when all lcd segments corresponding to com1, com2 and com3 are turned off. lcd driver output when only lcd segments corresponding to com1 are on. lcd driver output when only lcd segments corresponding to com2 are on. lcd driver output when lcd segments corresponding to com1 and com2 are on. lcd driver output when only lcd segments corresponding to com3 are on. lcd driver output when lcd segments corresponding to com1 and com3 are on. lcd driver output when lcd segments corresponding to com2 and com3 are on. lcd driver output when all lcd segments corresponding to com1, com2 and com3 are on. 1/3 duty, 1/3 bias waveforms vlcd vlcd1 vlcd2 0v fo[hz] vlcd vlcd1 vlcd2 0v vlcd vlcd1 vlcd2 0v vlcd vlcd1 vlcd2 0v vlcd vlcd1 vlcd2 0v vlcd vlcd1 vlcd2 0v vlcd vlcd1 vlcd2 0v vlcd vlcd1 vlcd2 0v vlcd vlcd1 vlcd2 0v vlcd vlcd1 vlcd2 0v vlcd vlcd1 vlcd2 0v note: when fc0 = 0, fc1 = 0, and fc2 = 0 in the control data f 0 = = f osc 768 f ck 768 when fc0 = 0, fc1 = 0, and fc2 = 1 in the control data f 0 = = f osc 576 f ck 576 when fc0 = 0, fc1 = 1, and fc2 = 0 in the control data f 0 = = f osc 384 f ck 384 when fc0 = 0, fc1 = 1, and fc2 = 1 in the control data f 0 = = f osc 288 f ck 288 when fc0 = 1, fc1 = 0, and fc2 = 0 in the control data f 0 = = f osc 192 f ck 192
no. 7980- 23 /39 lc75857e, lc75857w com1 1/4 duty, 1/2 bias drive technique com2 com3 com4 lcd driver output when all lcd segments corresponding to com1, com2, com3 and com4 are turned off. lcd driver output when only lcd segments corresponding to com1 are on. lcd driver output when only lcd segments corresponding to com2 are on. lcd driver output when lcd segments corresponding to com1 and com2 are on. lcd driver output when only lcd segments corresponding to com3 are on. lcd driver output when lcd segments corresponding to com1 and com3 are on. lcd driver output when lcd segments corresponding to com2 and com3 are on. lcd driver output when lcd segments corresponding to com1, com2 and com3 are on. lcd driver output when only lcd segments corresponding to com4 are on. lcd driver output when lcd segments corresponding to com2 and com4 are on. lcd driver output when all lcd segments corresponding to com1, com2, com3 and com4 are on. 1/4 duty, 1/2 bias waveforms vlcd vlcd1, vlcd2 0v fo[hz] vlcd vlcd1, vlcd2 0v vlcd vlcd1, vlcd2 0v vlcd vlcd1, vlcd2 0v vlcd vlcd1, vlcd2 0v vlcd vlcd1, vlcd2 0v vlcd vlcd1, vlcd2 0v vlcd vlcd1, vlcd2 0v vlcd vlcd1, vlcd2 0v vlcd vlcd1, vlcd2 0v vlcd vlcd1, vlcd2 0v vlcd vlcd1, vlcd2 0v vlcd vlcd1, vlcd2 0v vlcd vlcd1, vlcd2 0v vlcd vlcd1, vlcd2 0v note: when fc0 = 0, fc1 = 0, and fc2 = 0 in the control data f 0 = = f osc 768 f ck 768 when fc0 = 0, fc1 = 0, and fc2 = 1 in the control data f 0 = = f osc 576 f ck 576 when fc0 = 0, fc1 = 1, and fc2 = 0 in the control data f 0 = = f osc 384 f ck 384 when fc0 = 0, fc1 = 1, and fc2 = 1 in the control data f 0 = = f osc 288 f ck 288 when fc0 = 1, fc1 = 0, and fc2 = 0 in the control data f 0 = = f osc 192 f ck 192
no. 7980- 24 /39 lc75857e, lc75857w com1 1/4 duty, 1/3 bias drive technique com2 com3 com4 lcd driver output when all lcd segments corresponding to com1, com2, com3 and com4 are turned off. lcd driver output when only lcd segments corresponding to com1 are on. lcd driver output when only lcd segments corresponding to com2 are on. lcd driver output when lcd segments corresponding to com1 and com2 are on. lcd driver output when only lcd segments corresponding to com3 are on. lcd driver output when lcd segments corresponding to com1 and com3 are on. lcd driver output when lcd segments corresponding to com2 and com3 are on. lcd driver output when lcd segments corresponding to com1, com2 and com3 are on. lcd driver output when only lcd segments corresponding to com4 are on. lcd driver output when lcd segments corresponding to com2 and com4 are on. lcd driver output when all lcd segments corresponding to com1, com2, com3 and com4 are on. 1/4 duty, 1/3 bias waveforms fo[hz] vlcd vlcd1 vlcd2 0v vlcd vlcd1 vlcd2 0v vlcd vlcd1 vlcd2 0v vlcd vlcd1 vlcd2 0v vlcd vlcd1 vlcd2 0v vlcd vlcd1 vlcd2 0v vlcd vlcd1 vlcd2 0v vlcd vlcd1 vlcd2 0v vlcd vlcd1 vlcd2 0v vlcd vlcd1 vlcd2 0v vlcd vlcd1 vlcd2 0v vlcd vlcd1 vlcd2 0v vlcd vlcd1 vlcd2 0v vlcd vlcd1 vlcd2 0v vlcd vlcd1 vlcd2 0v note: when fc0 = 0, fc1 = 0, and fc2 = 0 in the control data f 0 = = f osc 768 f ck 768 when fc0 = 0, fc1 = 0, and fc2 = 1 in the control data f 0 = = f osc 576 f ck 576 when fc0 = 0, fc1 = 1, and fc2 = 0 in the control data f 0 = = f osc 384 f ck 384 when fc0 = 0, fc1 = 1, and fc2 = 1 in the control data f 0 = = f osc 288 f ck 288 when fc0 = 1, fc1 = 0, and fc2 = 0 in the control data f 0 = = f osc 192 f ck 192
voltage detection type reset circuit (vdet) this circuit generates an output signal and resets the system when logic block power is first applied and when the voltage drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection voltage vdet, which is 2.2v, typical. to assure that this function operates reliably, a capacitor must be added to the logic block power supply line so that the logic block power supply voltage v dd rise time when the logic block power is first applied and the logic block power supply voltage v dd fall time when the voltage drops are both at least 1 ms. (see figure 5 and figure 6.) power supply sequence the following sequences must be observed when power is turned on and off. (see figure 5 and figure 6.) power on :logic block power supply(v dd ) on ? lcd driver block power supply(v lcd ) on power off:lcd driver block power supply(v lcd ) off ? logic block power supply(v dd ) off however, if the logic and lcd driver block use a shared power supply, then the power supplies can be turned on and off at the same time. system reset the lc75857e/w supports the reset methods described below. when a system reset is applied, display is turned off, key scanning is stopped, and all the key data is reset to low. when the reset is cleared, display is turned on and key scanning become possible. 1. reset methods if at least 1 ms is assured as the logic block supply voltage v dd rise time when logic block power is applied, a system reset will be applied by the vdet output signal when the logic block supply voltage is brought up. if at least 1 ms is assured as the logic block supply voltage v dd fall time when logic block power drops, a system reset will be applied in the same manner by the vdet output signal when the supply voltage is lowered. note that the reset is cleared at the point when all the serial data (1/3 duty: the display data d1 to d126 and the control data, 1/4 duty: the display data d1 to d164 and the control data) has been transferred, i.e., on the fall of the ce signal on the transfer of the last direction data, after all the direction data has been transferred. (see figure 5 and figure 6.) no. 7980- 25 /39 lc75857e, lc75857w
no. 7980- 26 /39 lc75857e, lc75857w vdd ce vlcd vil1 t3 t2 t4 t1 vdet vdet d1 to d42, sp, kc0 to kc2, ksc, k0, k1,p0 to p2, sc, dr, dt, fc0 to fc2, oc internal data (d43 to d84) internal data (d85 to d126) internal data note: t1 3 1 [ms] (logic block power supply voltage v dd rise time) t2 3 0 t3 3 0 t4 3 1 [ms] (logic block power supply voltage v dd fall time) ? 1/3 duty vil1 t3 t2 t4 t1 vdet vdet vdd ce vlcd d1 to d44, sp, kc0 to kc2, ksc, k0, k1, p0 to p2, sc, dr, dt,fc0 to fc2, oc internal data (d45 to d84) internal data (d85 to d124) internal data internal data (d125 to d164) note: t1 3 1 [ms] (logic block power supply voltage v dd rise time) t2 3 0 t3 3 0 t4 3 1 [ms] (logic block power supply voltage v dd fall time) figure 6 ? 1/4 duty display and control data transfer undefined undefined undefined defined defined defined undefined undefined undefined system reset period display and control data transfer undefined undefined undefined undefined system reset period defined defined defined defined undefined undefined undefined undefined figure 5
no. 7980- 27 /39 lc75857e, lc75857w 2. lc75857e/w internal block states during the reset period clock generator a reset is applied and either the osc pin oscillator is stopped or external clock input is stopped. common driver, segment driver & latch reset is applied and the display is turned off. however, display data can be input to the latch circuit in this state. key scan reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled. key buffer reset is applied and all the key data is set to low. ccb interface, control register, shift register since serial data transfer is possible, these circuits are not reset. vdet ccb interface com4/s39 com3 com2 com1 common driver clock generator vss vlcd2 vlcd1 vlcd ce vdd di test cl do osc ki5 ki4 ki3 ki2 ki1 ks6 ks5 ks4 s42/ks3 s41/ks2 s40/ks1 key scan key buffer control register segment driver & latch s1/p1 s2/p2 s4/p4 s5 s38 s3/p3 shift register blocks that are reset
no. 7980- 28 /39 lc75857e, lc75857w 3. pin states during the reset period notes: * 5. these output pins are forcibly set to the segment output function and held low. * 6. when power is first applied, this output pin is forcibly set to the common output function and held low. however, when the dt c ontrol data bit is transferred, either the common output or the segment output function is selected. * 7. this output pin is forcibly held fixed at the low level. * 8. this i/o pin is forcibly set to the high-impedance state. * 9. since this output pin is an open-drain output, a pull-up resistor of between 1 and 10 k is required. this pin remains high during the reset period even if a key data read operation is performed. pin state during reset s1/p1 to s4/p4 l * 5 s5 to s38 l com1 to com3 l com4/s39 l * 6 ks1/s40 to ks3/s42 l * 5 ks4 to ks6 l * 7 osc z * 8 do h * 9 osc cosc rosc notes on the osc pin peripheral circuit 1. rc oscillator mode (control data bit oc = 0) when rc oscillator mode is selected, the external resistor rosc and the external capacitor cosc must be connected between the osc pin and ground. osc rg external clock output pin external oscillator 2. external clock mode (control data bit oc = 1) when external clock mode is selected, the current protection resistor rg (4.7 to 47 k ) must be connected between the osc pin and the external clock output pin (external oscillator). the value of this resistor is determined by the allowable current for the external clock output pin. verify that the external clock waveform is not deformed significantly. note: the external clock output pin allowable current must be greater than vdd/rg.
sample application circuit 1 1/3 duty, 1/2 bias (for use with normal panels) no. 7980- 29 /39 lc75857e, lc75857w +5v +3v * 1 0 c * 1 2 vdd s38 com4/s39 s5 p4/s4 p2/s2 p1/s1 com3 (p 1 ) (p2) (s4 1 ) (s42) (p4) com1 osc * 11 com2 do di cl ce vlcd1 vlcd2 vlcd test vss s 4 1 / k s 2 s 4 0 / k s 1 s 4 2 / k s 3 k s 4 k i 1 k i 2 k i 3 k i 4 k i 5 k s 5 k s 6 p3/s3 (s40) (p3) (general-purpose output ports) used with the backlight controller or other circuit. lcd panel (up to 126 segments) c 3 0.047 f from the controller to the controller to the controller power supply key matrix (up to 30 keys) notes: * 10. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the lc75857e/w is reset by the vdet. * 11. when rc oscillator mode is used, the external resistor rosc and the external capacitor cosc must be connected between the o sc pin and ground, and when external clock mode is selected the current protection resistor rg (4.7 to 47 k ) must be connected between the osc pin and the external clock output pin (external oscillator). (see the section on the osc pin peripheral circuit.) * 12. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1 to 10 k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
no. 7980- 30 /39 lc75857e, lc75857w sample application circuit 2 1/3 duty, 1/2 bias (for use with large panels) +5v +3v * 1 0 r r c * 1 2 vdd s38 com4/s39 s5 p4/s4 p2/s2 p 1/s1 com3 (p 1 ) (p2) (s4 1 ) (s42) (p4) com1 osc * 11 com2 do di cl ce vlcd1 vlcd2 vlcd test vss s 4 1 / k s 2 s 4 0 / k s 1 s 4 2 / k s 3 k s 4 k i 1 k i 2 k i 3 k i 4 k i 5 k s 5 k s 6 p3/s3 (s40) (p3) 10 k 3 r 3 1 k c 3 0.047 f (general-purpose output ports) used with the backlight controller or other circuit. lcd panel (up to 126 segments) from the controller to the controller to the controller power supply key matrix (up to 30 keys) notes: * 10. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the lc75857e/w is reset by the vdet. * 11. when rc oscillator mode is used, the external resistor rosc and the external capacitor cosc must be connected between the o sc pin and ground, and when external clock mode is selected the current protection resistor rg (4.7 to 47 k ) must be connected between the osc pin and the external clock output pin (external oscillator). (see the section on the osc pin peripheral circuit.) * 12. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1 to 10 k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
no. 7980- 31 /39 lc75857e, lc75857w sample application circuit 3 1/3 duty, 1/3 bias (for use with normal panels) +5v +3v * 1 0 c * 1 2 vdd s38 com4/s39 s5 p4/s4 p2/s2 p1/s1 com3 (p 1 ) (p2) (s4 1 ) (s42) (p4) com1 osc * 11 com2 do di cl ce vlcd1 vlcd2 vlcd test vss s 4 1 / k s 2 s 4 0 / k s 1 s 4 2 / k s 3 k s 4 k i 1 k i 2 k i 3 k i 4 k i 5 k s 5 k s 6 p3/s3 (s40) (p3) (general-purpose output ports) used with the backlight controller or other circuit. lcd panel (up to 126 segments) c 3 0.047 f from the controller to the controller to the controller power supply key matrix (up to 30 keys) c notes: * 10. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the lc75857e/w is reset by the vdet. * 11. when rc oscillator mode is used, the external resistor rosc and the external capacitor cosc must be connected between the o sc pin and ground, and when external clock mode is selected the current protection resistor rg (4.7 to 47 k ) must be connected between the osc pin and the external clock output pin (external oscillator). (see the section on the osc pin peripheral circuit.) * 12. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1 to 10 k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
no. 7980-32/39 lc75857e, lc75857w sample application circuit 4 1/3 duty, 1/3 bias (for use with large panels) +5v +3v * 1 0 c c r r r * 1 2 vdd s38 com4/s39 s5 p4/s4 p2/s2 p1/s1 com3 (p 1 ) (p2) (s4 1 ) (s42) (p4) com1 osc * 11 com2 do di cl ce vlcd1 vlcd2 vlcd test vss s 4 1 / k s 2 s 4 0 / k s 1 s 4 2 / k s 3 k s 4 k i 1 k i 2 k i 3 k i 4 k i 5 k s 5 k s 6 p3/s3 (s40) (p3) 10 k 3 r 3 1 k c 3 0.047 f (general-purpose output ports) used with the backlight controller or other circuit. lcd panel (up to 126 segments) from the controller to the controller to the controller power supply key matrix (up to 30 keys) notes: * 10. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the lc75857e/w is reset by the vdet. * 11. when rc oscillator mode is used, the external resistor rosc and the external capacitor cosc must be connected between the o sc pin and ground, and when external clock mode is selected the current protection resistor rg (4.7 to 47 k ) must be connected between the osc pin and the external clock output pin (external oscillator). (see the section on the osc pin peripheral circuit.) * 12. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1 to 10 k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
no. 7980- 33 /39 lc75857e, lc75857w sample application circuit 5 1/4 duty, 1/2 bias (for use with normal panels) +5v +3v * 1 0 c * 1 2 vdd s38 s39/com4 s5 p4/s4 p2/s2 p1/s1 com3 (p 1 ) (p2) (s4 1 ) (s42) (p4) com1 osc * 11 com2 do di cl ce vlcd1 vlcd2 vlcd test vss s 4 1 / k s 2 s 4 0 / k s 1 s 4 2 / k s 3 k s 4 k i 1 k i 2 k i 3 k i 4 k i 5 k s 5 k s 6 p3/s3 (s40) (p3) (general-purpose output ports) used with the backlight controller or other circuit. lcd panel (up to 164 segments) c 3 0.047 f from the controller to the controller to the controller power supply key matrix (up to 30 keys) notes: * 10. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the lc75857e/w is reset by the vdet. * 11. when rc oscillator mode is used, the external resistor rosc and the external capacitor cosc must be connected between the o sc pin and ground, and when external clock mode is selected the current protection resistor rg (4.7 to 47 k ) must be connected between the osc pin and the external clock output pin (external oscillator). (see the section on the osc pin peripheral circuit.) * 12. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1 to 10 k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
no. 7980- 34 /39 lc75857e, lc75857w sample application circuit 6 1/4 duty, 1/2 bias (for use with large panels) +5v +3v * 1 0 r r c * 1 2 vdd s38 s39/com4 s5 p4/s4 p2/s2 p1/s1 com3 (p 1 ) (p2) (s4 1 ) (s42) (p4) com1 osc * 11 com2 do di cl ce vlcd1 vlcd2 vlcd test vss s 4 1 / k s 2 s 4 0 / k s 1 s 4 2 / k s 3 k s 4 k i 1 k i 2 k i 3 k i 4 k i 5 k s 5 k s 6 p3/s3 (s40) (p3) 10 k 3 r 3 1 k c 3 0.047 f (general-purpose output ports) used with the backlight controller or other circuit. lcd panel (up to 164 segments) from the controller to the controller to the controller power supply key matrix (up to 30 keys) notes: * 10. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the lc75857e/w is reset by the vdet. * 11. when rc oscillator mode is used, the external resistor rosc and the external capacitor cosc must be connected between the o sc pin and ground, and when external clock mode is selected the current protection resistor rg (4.7 to 47 k ) must be connected between the osc pin and the external clock output pin (external oscillator). (see the section on the osc pin peripheral circuit.) * 12. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1 to 10 k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
no. 7980- 35 /39 lc75857e, lc75857w sample application circuit 7 1/4 duty, 1/3 bias (for use with normal panels) +5v +3v * 1 0 cc * 1 2 vdd s38 s39/com4 s5 p4/s4 p2/s2 p1/s1 com3 (p 1 ) (p2) (s4 1 ) (s42) (p4) com1 osc * 11 com2 do di cl ce vlcd1 vlcd2 vlcd test vss s 4 1 / k s 2 s 4 0 / k s 1 s 4 2 / k s 3 k s 4 k i 1 k i 2 k i 3 k i 4 k i 5 k s 5 k s 6 p3/s3 (s40) (p3) (general-purpose output ports) used with the backlight controller or other circuit. lcd panel (up to 164 segments) c 3 0.047 f from the controller to the controller to the controller power supply key matrix (up to 30 keys) notes: * 10. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the lc75857e/w is reset by the vdet. * 11. when rc oscillator mode is used, the external resistor rosc and the external capacitor cosc must be connected between the o sc pin and ground, and when external clock mode is selected the current protection resistor rg (4.7 to 47 k ) must be connected between the osc pin and the external clock output pin (external oscillator). (see the section on the osc pin peripheral circuit.) * 12. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1 to 10 k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
no. 7980- 36 /39 lc75857e, lc75857w sample application circuit 8 1/4 duty, 1/3 bias (for use with large panels) +5v +3v * 1 0 c c r r r * 1 2 vdd s38 s39/com4 s5 p4/s4 p2/s2 p1/s1 com3 (p 1 ) (p2) (s4 1 ) (s42) (p4) com1 osc * 11 com2 do di cl ce vlcd1 vlcd2 vlcd test vss s 4 1 / k s 2 s 4 0 / k s 1 s 4 2 / k s 3 k s 4 k i 1 k i 2 k i 3 k i 4 k i 5 k s 5 k s 6 p3/s3 (s40) (p3) 10 k 3 r 3 1 k c 3 0.047 f (general-purpose output ports) used with the backlight controller or other circuit. lcd panel (up to 164 segments) from the controller to the controller to the controller power supply key matrix (up to 30 keys) notes on transferring display data from the controller when using the lc75857e/w in 1/3 duty, applications transfer the display data (d1 to d126) in three operations, and in 1/4 duty, they transfer the display data (d1 to d164) in four operations. in either case, applications should transfer all of the display data within 30 ms to maintain the quality of the displayed image. notes: * 10. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the lc75857e/w is reset by the vdet. * 11. when rc oscillator mode is used, the external resistor rosc and the external capacitor cosc must be connected between the o sc pin and ground, and when external clock mode is selected the current protection resistor rg (4.7 to 47 k ) must be connected between the osc pin and the external clock output pin (external oscillator). (see the section on the osc pin peripheral circuit.) * 12. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1 to 10 k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
notes on the controller key data read techniques 1. timer based key data acquisition (1) flowchart (2) timing chart (3) explanation in this technique, the controller uses a timer to determine key on/off states and read the key data. the controller must check the do state when ce is low every t9 period without fail. if do is low, the controller recognizes that a key has been pressed and executes the key data read operation. the period t9 in this technique must satisfy the following condition. t9>t6+t7+t8 if a key data read operation is executed when do is high, the read key data (kd1 to kd30) and sleep acknowledge data (sa) will be invalid. no. 7980- 37 /39 lc75857e, lc75857w yes no do = [l] ce = [l] do di ce key on key on t6 t9 t9 t9 t9 t5 t8 t8 t7 t7 t5 t7 t8 t5 t5: key scan execution time when the key data agreed for two key scans. (615t(s)) t6: key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1230t(s)) t7: key address (43h) transfer time t8: key data read time 1 1 t = ?= fosc f ck key data read processing key input key scan key data read request key data read key address controller determination (key on) controller determination (key on) controller determination (key off) controller determination (key on) controller determination (key off)
no. 7980- 38 /39 lc75857e, lc75857w 2. interrupt based key data acquisition (1) flowchart (2) timing chart yes yes no do = [l] ce = [l] ce = [l] no do = [h] key off do di ce key on key on t10 t10 t10 t10 t5 t6 t8 t8 t7 t7 t5 t7 t8 t5 t7 t8 t5: key scan execution time when the key data agreed for two key scans. (615t(s)) t6: key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1230t(s)) t7: key address (43h) transfer time t8: key data read time 1 1 t = ?= fosc f ck key data read processing wait for at least t10 key input key scan key data read request key data read key address controller determination (key on) controller determination (key off) controller determination (key on) controller determination (key on) controller determination (key off) controller determination (key on)
ps no. 7980- 39 /39 lc75857e, lc75857w (3) explanation in this technique, the controller uses interrupts to determine key on/off states and read the key data. the controller must check the do state when ce is low. if do is low, the controller recognizes that a key has been pressed and executes the key data read operation. after that the next key on/off determination is performed after the time t10 has elapsed by checking the do state when ce is low and reading the key data. the period t10 in this technique must satisfy the following condition. t10 > t6 if a key data read operation is executed when do is high, the read key data (kd1 to kd30) and sleep acknowledge data (sa) will be invalid. this catalog provides information as of september, 2004. specifications and information herein are subject to change without notice. specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer?s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer?s products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the delivery specification for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

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